Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, organo-metallic decomposition, chemical vapor deposition, plasma vapor deposition, electrodeposition (electroplating) and other techniques. These layers are further processed by a variety of well-known etching technologies and subsequent deposition and polishing steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the various wiring or metallization layers that interconnect the individual circuits. Conventional metal deposition techniques include physical vapor deposition, sputtering and evaporation, and chemical vapor deposition techniques. Also, integrated circuit and equipment manufacturers have developed electrochemical deposition techniques, (including electroless and electrolytic plating) to deposit primary conductor films on various semiconductors (e.g., Si, GaAs), ceramics, printed circuit boards and a variety of other suitable substrates.
Integrated circuit wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM was the first to introduce copper damascene and dual damascene technology that facilitated a transition from aluminum to copper wiring layers. This technology demanded corresponding changes in process architecture, as well as new process technologies. Today, damascene processing is commonly used not only in the manufacture of integrated circuits, but also in memory fabrication; it is even displacing a variety of other back-end packaging applications, such as in printed circuit board manufacture.
For damascene integrated circuit and memory applications (where wiring is relatively close to the copper-sensitive silicon substrate), the conductive layers are typically deposited on a dielectric layer and typically comprise metals such as tantalum (Ta), tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), and alloys thereof, and semiconductors, such as doped silicon (Si), doped polysilicon, and refractory metal silicides. The three dimensional structure consist of multiple dielectric layers with openings, or feature cavities, (vias and trenches) that are filled with conductive material that provide circuit paths through dielectric material within and between the various layers and and eventually to transistor circuit devices. After the deposition of metal at each level, the conductive layer is typically polished, and only the conductive material filling the feature cavities remains in the dielectric layer.
A typical damascene or dual damascene process flow scheme for fabricating copper interconnects, such as copper lines and vias, typically includes: forming a trench pattern on a layer dielectric layer using an etch-resistant photoresist; etching a trench pattern; removing the photoresist; forming a via pattern on a dielectric material using etch resistant photoresist; etching vias; removing resist; depositing a barrier (e.g., tantalum, tantalum nitride, combinations of these) and a copper seed layer (e.g., using plasma vapor deposition, PVD); electroplating copper to fill the etched feature cavities; and polishing copper and barrier off the wafer face leaving copper-filled electrically isolated interconnect circuitry.
As the number of levels in an interconnect technology increases, the stacking of additional layers produces more rugged and complex topography. Compounding this problem, electroplating bath additives are now commonly utilized to promote rapid “bottom-up” filling of high aspect-ratio features in damascene copper electroplating processes to ensure complete void-free metal fill of high aspect ratio features (features deeper than they are wide). Baths with good “bottom-up” filling characteristics fill high aspect ratio features more rapidly and without creating voids or seams when compared to baths with less effective combinations of such additives. While the action of plating bath additives is still a subject of active investigation, it is now generally accepted that bottom-up filling of high aspect ratio features is controlled by the geometrical concentration of a strongly adsorbed plating bath “accelerator” bound within and on the walls of the feature. As a metal film within the feature grows, the surface area decreases within the feature and concentrates the adsorbate, lowering the resistance to charge transfer in the feature compared to the flatter exposed regions of the surface, thereby creating an “acceleration” of the plating rate within the recessed feature region. (See, for example, J. Osterwald and J. Schulz-Harder, Galvanotechnik, 66, 360 (1975), J. Osterwald, Oberflache-Surface, 17, 89, (1976), J. Reid and S. Mayer, in Advanced Metallization Conference, 1999, M. E. Gross, T. Gessner, N. Kobayashi, and Y. Yauda, Editors, pg 53, MRS, Warrendale, Pa. (2000), A. C. West, S. Mayer, and J. Reid, Electrochem. Solid-State Letters, 4, C50, (2001), T. P. Moffat, D. Wheeler, and D. Josell, “Superfilling and the Curvature Enhanced Accelerator Coverage Mechanism, The Electrochemical Society Interface, Winter, 2004). Therefore, baths with good “bottom-up” filling characteristics typically fill smaller (higher aspect ratio) features more rapidly than larger (lower aspect ratio) features because their surface to volume ratio is larger. In some cases (e.g., plating baths with superior bottom-up filling characteristics and little or no leveling additives), plating continues at an accelerated rate after completing the small-feature filling stage. When many high-aspect ratio features are located in close proximity, the amount of adsorbed accelerator originally associated with the high surface area of that region remains after the features have filled. Hence, growth continues at an accelerated rate beyond the point of features-fill and into a period in which metal between the features has merged. When this happens, a macroscopic raised area forms over the entire region of underlying high aspect ratio features, initially as a series of thicker metallized bumps, and after they merge, as a raised plateau. This formation of raised topography is also termed “feature overplating” or “momentum plating”.
The use of advanced “bottom-up” electrofilling techniques with wafers having low and high aspect-ratio features has created a problem of deposited metal surfaces with a wide range of topography, that is, topography containing a large range or aspect ratios of both recessed and raised areas. Commonly, features vary in width by two to three orders of magnitude on a single layer. As a specific example, a 0.5 μm-deep (thick dielectric) level can have feature widths of from 0.1 μm to 100 μm. Therefore, while electroplating is the preferred method of metallization, various aspects of improved plating regimens create challenging topography for subsequent planarization
A principal objective of damascene circuit interconnect fabrication is to create metal isolated by and embedded in a dielectric medium. The preferential filling of recessed features in modern bottom-up electroplating techniques requires careful control of process conditions. U.S. Pat. No. 6,946,065, titled “Process for Electroplating Metal into Microscopic Recessed Features”, issued Sep. 20, 2005 to Mayer et. al., which is hereby incorporated by reference for all purposes, teaches techniques for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. For the most part, prior processes are largely isotropic and do not preferentially fill and planarize low-aspect-ratio features and therefore they require significant excess metal deposition (“overburden.”) Overburden is the additional copper deposited on the substrate to ensure that all low-aspect-ratio features are completely filled (essentially in an isotropic fashion) to the plane of a base layer, that is, to the plane of the isolating dielectric surface (the “field”). Since the preferential “bottom-up” filling generally does not occur in low-aspect-ratio features, the surface of the overburden above low-aspect-ratio features typically follows the contours within the dielectric and of the underlying low-aspect-ratio features. In most cases, the overburden on field regions is slightly thicker than the thickness of the damascene dielectric layer, typically on the order of 1.2 times the depth of the deepest feature. So, for example, a damascene structure that has 0.5 micrometers (μm) deep features typically requires an overburden of at least approximately 0.7 to 0.8 micrometers.
Overburden is undesirable for a number of reasons. It requires deposition of considerable amounts of excess copper over the field that is essentially wasted andit requires extra effort associated with removing the overburden material. Thus, overburden represents additional materials costs (excess copper deposited and removed), as well as decreased throughput and productivity. In current processes, overburden is removed by a planarization technique such as chemical mechanical polishing (CMP), electrochemical chemical polishing (eCMP), or electropolishing. CMP and eCMP are particularly expensive processes that generally use corrosive chemical and slurry formulations on large (wafer scale or larger) pads to polish the surface of the integrated circuit substrate. Such pad-rubbing processes are often difficult to control and the polishing end-point can be difficult to detect. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP and eCMP. Also, with the introduction of porous low-k dielectrics in semiconductor devices, modification of traditional CMP and even eCMP processes is required, as current methods can crack and/or delaminate low-k materials, which typically have a very low compression strength and extreme fragility. Furthermore, none of these techniques achieve perfect planarization at all length scales.
Relatively large copper lines in electronic equipment, for example, in a printed wiring board (“PWB”), are typically formed by a process including lamination, photolithography, screen-printing, and wet etching.
Another method of patterning copper lines, which was also commonly used for making small lines until the invention of the damascene process, is through-resist plating. In this technique, a metal seed layer is first deposited to cover completely a base plane substrate, resist is applied over the seed layer, and areas to be plated-up are optically exposed and developed (wherein the resist is removed to expose copper seed at the base). Thereafter, during electroplating, metal is deposited only in the exposed and developed areas. In such a technique, copper can be plated controllably only to the thickness of the resist. If additional copper is plated, it is no longer confined by the walls of the lines defined by the resist, and will tend to grow laterally and encroach into other lines due to the loss of confinement and due to plating both upwards and sideways. Also, in such techniques, the plating solution contacts the resist. As a result of leaching of organic electroactive contamination from the resist, the lifetime of the plating solution is often reduced, adding cost to the overall process. A damascene process is well suited for producing lines of small depth (or height or thickness) in features having high aspect ratio, but is prohibitively expensive for thick copper layers due to the high cost of removing copper from the insulating dielectric surface (“field”). In a damascene process, copper plates onto the field area to a thickness corresponding to the desired height (or thickness) of the wiring line, and all of this excess copper must be removed by chemical mechanical planarization in order to form the copper line.
FIGS. 1A-1F depict schematically a sequence of process phases of a generalized method of forming a metal feature embedded in a dielectric layer using conventional photoresist techniques of the prior art. FIG. 1A depicts a cross-sectional view 10 of substrate section 12 including base dielectric layer 14 covered by photoresist layer 16. FIG. 1B depicts an intermediate stage 20 of fabrication after patterning and etching of photoresist 16 to expose surface portion 22 of dielectric layer 14. FIG. 1C depicts an intermediate stage 30 after etching of exposed area 22 (FIG. 1B) to form recessed cavity 32 in dielectric layer 14. FIG. 1D depicts further intermediate stage 40 in which the remnants of resist layer 16 have been removed from substrate section 12 prior to metallization processes. It is understood that in some methods, metallization processes are conducted without removing resist. FIG. 1E depicts further intermediate stage 50 in which metal seed layer 52 and electroplated copper layer 54 have been deposited on substrate section 12 using techniques known in the art. FIG. 1F depicts process stage 60 in which field metal has been etched and polished from substrate section 12 resulting in metal feature 62 embedded in base dielectric layer 14.
None of the techniques described is ideally suited to the production of small or large metal features, such as copper lines, interlevel connections, metal pads, and device connectors, and each technique incurs considerable costs associated with consumed material and waste disposal. Therefore, it would be desirable to have a technique for depositing copper or other metal wiring that would create the desired wiring without the need to add, pattern and remove dielectric or photoresist layers, and without the need to remove a large amount of copper (or other metal), and that would avoid electrolyte contamination associated with through-resist plating, allowing for longer plating bath lifetimes. Preferably, a technique for forming large copper lines would not have to be defined through etching of vias and trenches in a dielectric.
Osterwald et al., in “Wirkung von Badzusatzen bei der kathodischen Metallabscheidung”, Galvanotechnik, 66, Nr. 5, pp. 360-365 (1975), Leuze Verlag, Saulgau, Germany, and “Leveling and Roughening by Inhibitors and Catalysts” Oberfläche-Surface, 17, 89, (1976), teach an additive in solution that absorbs onto a cathode surface. The absorbed additive acts as a catalyst of metal deposition thereby increasing a metal deposition rate. The relative catalytic effect is related to the surface concentration of the adsorbate. Due to geometrical considerations, when the catalyzing additive is absorbed onto a surface having a recess, the surface concentration of catalyzing additive in the recess increases compared to its concentration in non-recessed areas as metal deposition proceeds. As a result, the rate of metal deposition in the recess becomes greater than the metal deposition rate at non-recessed areas. This leads to relative planarization of the deposited metal compared to topography resulting from metal plating on a substrate without adsorbed catalyzing additive. Later, others confirmed that specific chemical additives exhibit this behavior, and this behavior is conceptually useful in interpreting, modeling and controlling preferential filling of small damascene features. (See, for example, J. Reid and S. Mayer, in Advance Metallization Conference Proceedings, 1999, p. 53; A. C. West, S. Mayer, and J. Reid, Electrochem. Solid-State Lett., 4, C50, [2001]; T. P. Moffat, D. Wheeler, W. H. Huber, and D. Josell, Electrochem Solid State Lett, 4, C26, [2001]; and T. P. Moffat, D. Wheeler, and D. Josell, Electrochemical Society Interface, p. 46, Winter 2004). U.S. patent application Ser. No. 10/739,822, filed Dec. 17, 2003, by Mayer et al., having the title “Method for Planar.Electroplating”, teaches a method of selectively attaching a plating accelerator to recessed regions of the dielectric layer before electroplating to achieve selectively accelerated plating (SAP) of metal in the recessed regions.
There exists a need for improved technology for depositing conductive wiring embedded in dielectric substrates having varying feature sizes, particularly having both very narrow (submicron) and very wide (on the order of 100 μm) feature widths.